Often, different interrupt sources are assigned different priorities. the time needed for the ISR to do its work, especially if ISRs cannot preempt each other and so concurrent interrupts have to be serialized.Obviously, code, data and TLB caches are going to contribute here. the interrupt vector table, but there may be segment tables and page tables and others), the stack (the interrupted code instruction pointer will be typically saved on the stack, so the ISR can return to it), the ISR code itself and all the data it uses). the speed with which the CPU can access the needed memory (system tables (e.g.the CPU clock rate (often, events (or responses to them) occur no faster than that).latencies in the hardware of the CPU and the interrupt controller (if any).
0 kommentar(er)
